Witam

Szukając informacji o pamięciach SIMM, dotarłem do informacji że moduły 30 i 72 pinowe mają 12 linii adresowych, na czym robią 24 bity adresu. Czy ktoś mógłby mnie wytłumaczyć jak robią taką magię?

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2

to address multiplexing,  podaje dwa razy po 12 bit(rząd, columna) najlepiej wyjasnione na 30 pinowych modułach, źródło (post by trag)

https://www.macgurus.com/forums/archive … 17827.html

czyli w skrócie:

On early 30 pin SIMMs there were 12 possible address lines or wires. Each address line can represent a 1 or a 0, they are an electrical representation of a binary number. So if we have twelve digits, and we're using base 2 (binary), how high can we count? 4096. Not very high. So how do you get a 16MB SIMM with only 12 address lines?

Simple, the computer sends a 12 bit (binary digits) address. Then the computer sends another 12 bit binary address. The memory gathers them up, strings them together and makes a 24 bit number out of them. This is called address multiplexing. A 24 bit number provides 2^24 or ~16M addresses.

30 pin SIMMs are one byte wide, so 16M addresses yields 16MB of capacity per SIMM.

What is width? When the computer gives the RAM an address, there is more than 1 bit of data stored at that address. How many bits? That's the data width. A 30 pin SIMM is 8 bits wide or one byte wide (eight bits to a byte). If your computer (such as the Mac II family) uses four 30 pin SIMMs at a time, then it is putting them together to get more width, in this case 4 X 8 = 32 bits of data width.

So a 30 bit SIMM has 12 address lines and is 8 bits wide. From this we deduce that the maximum capacity is 2^(12 X 2) X 8 = 16MB. The (12 X 2) is simply 12 address bits times 2 because of the multiplexing. Then we figure the total number of addresses from the number of address bits using the 2^. And X8 takes care of the eight bit width.

The first 12 address bits are called the Row address. The second 12 address bits are called the Column address. When the computer is delivering the Row address it also activates the Row Address Strobe (RAS) wire. When the computer is delivering the Column address it activates the Column Address Strobe (CAS) wire. You may have seen RAS and CAS before when reading about refresh.

So, a memory module has RAS and CAS wires in addition to address wires (12 so far) and data wires (8 so far).

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Ach so.... dzięki za wyjaśnienie :D

Atari: FireBee, (Falcon030 CT60e SuperVidel SvEthlana CTPCI), TT, (520ST Pak030 Frak PuPla Panther), (520ST 4MB ST RAM 8MB TT RAM CosmosEx SC1435), (1040STFM UltraSatan SM124), (1040STE 4MB ST RAM 8MB TT RAM CosmosEx NetUSBee SM144 SC1224), 260ST, 520 ST+, (MEGA ST SM125), (65XE Rapidus U1MB VBXE SIDE2 SIO2PC), (Jaguar SkunkBoard), Lynx II, 2x Portfolio