Around August, 1978, one of MOS Technologies' second sources,
Synertek, began circulating specifications for a new 6500
microprocessor called the 6516. This chip was a pseudo-sixteen bit
processor designed to compete with the new Motorola 6809
microprocessor. This chip introduced a few new addressing modes and
several new instructions. Probably the most unique thing about it was
that it used a set processor status register bits to control whether or
not the A, X, and Y registers, or memory operands operated in eight or
sixteen bit mode. The (previously) unused bit in the P register became a
user flag in the 6516. The 6516 sported sixteen-bit accumulator, X, Y,
PC, and SP registers. It also incorporated an eight-bit "Z" register
which controlled the location of the zero page.
In terms of addressing modes, the 6516 supported the following
addressing modes:
- immediate,
- implied,
- register,
- direct page,
- direct page indirect,
- direct page indexed by X,
- direct page indexed by Y,
- direct page indexed by X indirect,
- direct page indirect indexed by Y,
- absolute, absolute indexed by X,
- absolute
- absolute indirect
- absolute indexed by X
- absolute indexed by Y
- 8 and 16 bit relative
The instruction set included all of the 6502's instructions plus LDZ
(STZ), LDS (load SP), LHA (load H.O. A byte), LHX (load H.O. X byte),
LHY (load H.O. Y byte), LAX (load A from location pointed at by X), SAX
(store A at (X)), LAY/SAY (load/store A at (Y)), ADD (no need to clear
carry), SUB (no need to set carry), INC/DEC accumulator, TAZ (init Z
register), TZA (get current Z register value), YPC (transfer Y to PC --
JMP (Y)), PCY (copy current PC into Y), XHA/XHX/XHY (swap A, X,
and Y halves), XXY (exchange values in X/Y registers), SEF/CLF
(set/clear user flag), LDQ (load "Q" processor register with an
immediate value), SEV (set overflow flag), AXA/AYA (add X/Y to A),
AAX/AAY (add A to X or Y), AMX/AMY (add memory to X or Y), NEG
(negate accumulator), several new shift and rotate instructions including
RLT, RRT, ASR, RHL, RHR, RXL, RXR, RYL, and RYR, BFS/BFC (branch if
user flag set/clear), JNE/JEQ (jump long if not equal/equal), PHD/PLD
(push/pop 16-bit A), PHX/PHY/PLX/PLY/PHZ/PLZ (push/pop X, Y, and
Z registers), PHR/PLR (push/pop all registers), BR1..BR5 (five new
BRK/software interrupt instructions).
In addition to the new instructions, Synertek enhanced several old
instructions by adding new addressing modes. They also reduced the
number of cycles needed to execute various instructions, for example,
many implied addressing mode instructions took only one cycle (rather
than two) on the 6516.
After reading over the Synertek technical notes, I immediately
wrote an article for Micro, the 6502 Journal discussing the 6516
microprocessor. The very next month after publication one of
Synertek's representatives wrote a letter to Micro swearing up and
down that there was no such project, never was such a project, and that
I'd made the whole thing up. Funny, I still have in my possession, on
Synertek letterhead, technical notes #34 and #40 which describe the
features of the SY6516 microprocessor.
The SY6516 never saw the light of day. Synertek's representatives
who had come around and shown me the specs for the SY6516 were
simply gauging people's reactions to the chip. Apparently, the reactions
weren't strong enough to forge ahead with the product. An advanced
65xx processor was not forthcoming from Synertek.
