The programmable input/output block (PIO) is a versatile hardware interface. It can support a variety of IO standards,
including:
• 8080 and 6800 parallel bus
• I2C
• 3-pin I2S
• SDIO
• SPI, DSPI, QSPI
• UART
• DPI or VGA (via resistor DAC)

PIO is programmable in the same sense as a processor. There are two PIO blocks with four state machines each, that can
independently execute sequential programs to manipulate GPIOs and transfer data. Unlike a general purpose processor,
PIO state machines are highly specialised for IO, with a focus on determinism, precise timing, and close integration with
fixed-function hardware. Each state machine is equipped with:
• Two 32-bit shift registers – either direction, any shift count
• Two 32-bit scratch registers
• 4×32-bit bus FIFO in each direction (TX/RX), reconfigurable as 8×32 in a single direction
• Fractional clock divider (16 integer, 8 fractional bits)
• Flexible GPIO mapping
• DMA interface, sustained throughput up to 1 word per clock from system DMA
• IRQ flag set/clear/status

Each state machine, along with its supporting hardware, occupies approximately the same silicon area as a standard
serial interface block, such as an SPI or I2C controller. However, PIO state machines can be configured and reconfigured
dynamically to implement numerous different interfaces.
Making state machines programmable in a software-like manner, rather than a fully configurable logic fabric like a CPLD,
allows more hardware interfaces to be offered in the same cost and power envelope. This also presents a more familiar
programming model, and simpler tool flow, to those who wish to exploit PIO’s full flexibility by programming it directly,
rather than using a premade interface from the PIO library.
PIO is highly performant as well as flexible, thanks to a carefully selected set of fixed-function hardware inside each state
machine. When outputting DPI, PIO can sustain 360 Mb/s during the active scanline period when running from a 48 MHz
system clock. In this example, one state machine is handling frame/scanline timing and generating the pixel clock, while
another is handling the pixel data, and unpacking run-length-encoded scanlines.
State machines' inputs and outputs are mapped to up to 32 GPIOs (limited to 30 GPIOs for RP2040), and all state
machines have independent, simultaneous access to any GPIO. For example, the standard UART code allows TX, RX, CTS
and RTS to be any four arbitrary GPIOs, and I2C permits the same for SDA and SCL. The amount of freedom available
depends on how exactly a given PIO program chooses to use PIO’s pin mapping resources, but at the minimum, an
interface can be freely shifted up or down by some number of GPIOs.